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| Ceramic Package Ceramic Leadless Chip Carrier Packages (CLCC) 0.010 S E H S D D3 J20.B 20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL A A1 B B1 E3 E MILLIMETERS MIN 1.78 1.37 0.51 MAX 2.46 1.96 0.76 NOTES 6, 7 2, 4 2 2 2 5 5 3 3 3 Rev. 0 5/18/94 j x 45 o MIN 0.070 0.054 0.020 MAX 0.097 0.077 0.030 B B2 B3 D D1 0.072 REF 0.006 0.342 0.022 0.358 1.83 REF 0.15 8.69 0.56 9.09 0.200 BSC 0.100 BSC 0.325 0.342 0.335 0.358 5.08 BSC 2.54 BSC 8.26 8.69 8.51 9.09 h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1 D2 D3 E E1 E2 E3 0.200 BSC 0.100 BSC 0.325 0.335 5.08 BSC 2.54 BSC 8.26 8.51 -E- e e1 h 0.050 BSC 0.015 - 1.27 BSC 0.38 1.02 REF 0.51 REF 1.07 1.07 1.91 0.08 5 5 20 1.47 1.47 2.41 0.38 0.040 REF 0.020 REF 0.042 0.042 0.075 0.003 5 5 20 0.058 0.058 0.095 0.015 0.007 M E F S H S B1 j L e L -HL3 L1 L2 L3 ND NE -FE1 B3 N NOTES: E2 L2 B2 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. L1 e1 D1 D2 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension "A" controls the overall package thickness. The maximum "A" dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. 33 |
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